[13] J. Duato. A Necessary and Sufficient Condition for

This paper presents a simple, efficient and cost effective routing strategy that considers deadlock recovery as opposed to prevention. Performance is optimized in the absence of deadlocks by allowing maximum flexibility in routing. Disha supports true fully adaptive routing where all virtual channels at each node are available to packets without regard for deadlocks. Deadlock cycles, upon forming, are efficiently broken by progressively routing one of the blocked packets through a deadlock-free lane. This lane is implemented using a central “floating” deadlock buffer resource in routers which is accessible to all neighboring routers along the path. Simulations show that the Disha scheme results in superior performance and is extremely simple, ensuring quick recovery from deadlocks and enabling the design of fast routers. 1.0 Introduction: The interconnection network is the backbone for communication in a multiprocessor/multi-computer environment. System performance is determined not only by the effective utilization of multiple processor nodes, but also, to a large extent, by efficient communication amongst the nodes. For this reason, many schemes have been proposed which incorporate wormhole switching [21] and adaptive routing [16] to increase communication efficiency. In such schemes, the critical issue of deadlocks must be addressed. Deadlocks in routing occur as a result of cyclic waits for network resources by packets. Avoidance has been the traditional solution to deadlocks. Schemes based on deadlock avoidance generally suffer from losses in adaptivity and/or increased hardware complexity which negatively impact performance. Consider first how adaptivity can suffer. The Turn Model [20], which does not require virtual channels, prevents deadlock by prohibiting those turns that could result in the formation of cycles in the channel dependency graph [9]. As a result, the adaptivity of routing algorithms based on the Turn Model is limited. The West-first algorithm, for example, demands that all packets be routed non-adaptively west first before they can be routed adaptively in other directions. Hence, if packets encounter congestion along the west direction, they must block, resulting in poor performance. Simulation studies show that such schemes produce unbalanced traffic conditions and often are outperformed even by non-adaptive algorithms [8]. Such partially adaptive schemes also cannot be fault tolerant. Another partially adaptive deadlock avoidance scheme is Planar-Adaptive Routing[4], which requires three virtual channels for n-dimensional mesh networks. It ensures deadlock freedom by restricting adaptivity to at most two dimensions at a time and structuring the passage of packets from one adaptive plane to another. Again, adaptivity suffers because some idle channels along minimal paths in the n-2 other dimensions are automatically excluded by the routing algorithm since they lie outside of the adaptive plane. To increase adaptivity, Linder and Harden [19] proposed a fully adaptive deadlock avoidance routing algorithm that requires an exponential growth (based on dimensionality) in the number of virtual channels to eliminate cycles in the channel dependency graph. Even with this large number of virtual channels, only a small subset of those channels are available to each packet as they are grouped into ordered levels or classes. Dally and Aoki’s Static Routing Algorithm [11] is similar in that it, too, groups virtual channels into ordered classes based on packet dimension reversals (higher to lower dimension traversals). This restricted use of virtual channels to ensure proper ordering for deadlock avoidance results in inefficient use of resources and, hence, falls well short of true full adaptivity. Consider next how avoidance schemes can increase hardware complexity. Increasing adaptivity (for deadlock avoidance routing) by adding additional virtual channels generally results in increased router switch and Virtual Channel Controller (VCC) complexity. A study by Chien [5] shows that the increased complexity adversely affects machine performance by increasing router clock cycle time. In fact, deterministic schemes could outperform certain adaptive schemes which require many virtual channels. This An Efficient, Fully Adaptive Deadlock Recovery Scheme: DISHA * Anjan K. V. Timothy Mark Pinkston Electrical Engineering Systems Department, University of Southern California 3740 McClintock Avenue, EEB-208, Los Angeles, CA 90089 2562 {anjan@truth, tpink@charity}.usc.edu; http://www.usc.edu/dept/ceng/faculty.html/pinkston/home.html * The research described in this paper was supported in part by an NSF Research Initiation Award, grant ECS-9411587, and by a grant from the Zumberg Fund and the Powell Fund. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, June 1995.